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INTEGRATED CIRCUITS
DATA SHEET
SAA8110G Digital Signal Processor (DSP) for cameras
Preliminary specification File under Integrated Circuits, IC02 1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
FEATURES * High precision digital processing with 9 or 10 bit input * Different types of CCDs (PAL, NTSC and CIF) (progressive, interlaced and non-interlaced) * Black offset preprocessing (including optical black offset control) * RGB-separation (with contour and white clip signals generation) * RGB-processing (colour space matrix, black control, knee and gamma) * RGB-to-YUV conversion (including down-sampling filters) * White balance control * Y-processing (contour processing, false colour detector, filters and noise reduction) * UV-processing (false colour correction and noise reduction) * Digital output formatter (including CIF-formatter, DTV2, D1) * Analog output preprocessing (including PAL/NTSC-encoder and DACs) * Measurement engine (prepared for auto-exposure and auto-white balance features) * Miscellaneous functions (e.g. switched mode power supply pulse generator, control DAC) * VH-reference and window timing * Serial interface (selectable I2C-bus or 80C51 UART interface) * Mode control (including power management). APPLICATIONS * Desktop video applications * Surveillance systems * Video-phone systems. ORDERING INFORMATION TYPE NUMBER SAA8110G PACKAGE NAME LQFP80 DESCRIPTION GENERAL DESCRIPTION
SAA8110G
The SAA8110G is designed for desktop video applications (teleconferencing, video grabbing), surveillance and video-phone systems. The SAA8110G may be applied together with an analog front-end (TDA8786 including CDS/AGC/ADC), a timing generator and a microcontroller as shown in Figs 18 and 19. Other configurations are also possible. The CCD-sensor can be of PAL, NTSC or CIF type (with complementary mosaic colour filter). The maximum number of active pixels is limited to 800 samples/line. The 10-bits digital input may have a pixel frequency of up to 14.318 MHz. The SAA8110G output data is available in a digital and an analog output format. Two digital output formats are selectable: DTV2 (CCIR-601 at the input pixel frequency) and D1 (CCIR-656 at twice the input pixel frequency). It is also possible to generate the CIF and QCIF formats as subsets from the processed CCD-image. The analog output is available in one of four formats: RGB, YUV, YC or CVBS. The SAA8110G includes a digital PAL/NTSC-encoder and 3 DACs for this purpose. Two types of serial interface are selectable: a fast 400 kHz I2C-bus interface or a 80C51 UART interface (with bit rates from 1 Mbit/s up to 3.75 Mbit/s depending on the system clock used). The power dissipation of the SAA8110G can be optimized for each application using the built-in power management function.
VERSION SOT315-1
plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
1997 Jun 13
2
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
QUICK REFERENCE DATA SYMBOL VDDD VDDA VIL VIH VOL VOH IDDD(tot) IDDA(tot) Tamb IDMD PARAMETER digital supply voltage analog supply voltage LOW level digital input voltage HIGH level digital input voltage LOW level digital output voltage IOL = -20 A HIGH level digital output voltage IOH = 20 A total digital supply current total analog supply current operating ambient temperature supply current in digital output mode fclk = 14.3 MHz; VDDD = 5 V; note 1 fclk = 14.3 MHz; VDDD = 5 V fclk = 14.3 MHz; VDDA = 5 V CONDITIONS 3 3 0 0.6VDDD - - - 0 - MIN. 5 5 - - - 180 80 30 22 - 185 85 TYP.
SAA8110G
MAX. 5.25 5.25 0.3VDDD VDDD 0.5 - 200 100 40 35 75 - -
UNIT V V V V V V mA mA mA mA C mA mA
VDDD - 0.1 -
fclk = 14.3 MHz; VDDD = 3.3 V - fclk = 14.3 MHz; VDDA = 3.3 V -
fclk = 14.3 MHz; VDDD = 3.3 V - Note 1. When digital mode is selected, VDDA supply pins can be connected to ground.
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VDDA(BG) VDDA(DC) VDDA(CD) VDDA(O1) VDDA(O2) VDDA(O3) VSSA(CD) VSSA(OB) VSSA(BG) 19, 34, 42 70 to 63 Y0 to Y7 61 to 54 UV0 to UV7 35, 37, 39 OUT3 to OUT1 43 44 79 80 49 50 48 52 51 28 DECOUPL RBIAS YPROCESSING UVPROCESSING DIGITAL OUTPUT FORMATTER 45, 41, 22, 40, 38, 36 6, 17, 76, 78, 53, 71 RGB PROCESSING RGB TO YUV
BLOCK DIAGRAM
Philips Semiconductors
VDDD(C1) VDDD(C2) VDDD(C3) VDDD(P1) VDDD(P2)
VSSD(C1) VSSD(C2) VSSD(C3) VSSD(C4) VSSD(P1) VSSD(P2)
1, 29,72, 46, 62
CCD9 to CCD0
7 to 16
OFFSET PREPROCESSING
RGB SEPARATION (INCL. LINE MEMORIES)
Digital Signal Processor (DSP) for cameras
CLK1
2 MEASUREMENT ENGINE
ANALOG OUTPUT PREPROCESSING PAL/NTSCENCODER V DACs
XIN XOUT VSYNCOUT HREF FIOUT LLC CREF/PXQ
CLK2
47
4
SAA8110G
MISCELLANEOUS FUNCTIONS VH-REFERENCE WINDOW TIMING AND CONTROL SNERT/I2C INTERFACE SNERT/ I2C SELECT 20 SMP SCLK HSYNCIN VSYNCIN FIIN P0, P1 STROBE SDATA 21 25 26, 27 23 24 18 3 4 5 73 A1/SNRES 77 75 SDA SCL/SNCL A0/SNDA 74
31 to 33
T2, T1, T0
MODE CONTROL
SIS
RESET
30
MGK158
CDACOUT
CDACRBIAS
Preliminary specification
SAA8110G
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
PINNING SYMBOL VDDD(C1) CLK1 VSYNCIN HSYNCIN FIIN VSSD(C1) CCD9 CCD8 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VSSD(C2) SCLK VSSA(CD) CDACOUT CDACRBIAS VDDA(CD) SDATA STROBE SMP P0 P1 SIS VDDD(C2) RESET T2 T1 T0 VSSA(OB) OUT3 VDDA(O3) OUT2 VDDA(O2) OUT1 VDDA(O1) 1997 Jun 13 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I I I I I I I I I I I I I O I O I I O O O O O I I I I I I I O I O I O I system- or pixel clock vertical synchronization input horizontal synchronization input field identification signal input digital ground 1 for digital core and CLK1 related peripherals (preprocessed) AD-converted CDD-signal bit 9 (MSB) (preprocessed) AD-converted CDD-signal bit 8 (preprocessed) AD-converted CDD-signal bit 7 (preprocessed) AD-converted CDD-signal bit 6 (preprocessed) AD-converted CDD-signal bit 5 (preprocessed) AD-converted CDD-signal bit 4 (preprocessed) AD-converted CDD-signal bit 3 (preprocessed) AD-converted CDD-signal bit 2 (preprocessed) AD-converted CDD-signal bit 1 (preprocessed) AD-converted CDD-signal bit 0 (LSB) digital ground 2 for digital core and CLK1 related peripherals serial clock to TDA8786 analog ground for control DAC output control DAC pin to connect external bias resistor for control DAC analog supply for control DAC serial data to TDA8786 strobe to TDA8786 switch mode pulse for DC-DC quasi-static control output pin 0 quasi-static control output pin 1 SNERT/I2C-bus select input signal digital supply 2 for digital core and CLK1 related peripherals reset input test mode control signal bit 2 test mode control signal bit 1 test mode control signal bit 0 analog ground for the three output buffers output buffer 3 (R, V or CVBS) analog supply for output buffer OUT3 output buffer 2 (B, U or C) analog supply for output buffer OUT2 output buffer 1 (G or Y) analog supply for output buffer OUT1 5 DESCRIPTION digital supply 1 for digital core and CLK1 related peripherals
SAA8110G
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SYMBOL VDDA(DC) VSSA(BG) DECOUPL RBIAS VDDA(BG) VDDD(P1) CLK2 FIOUT VSYNCOUT HREF CREF/PXQ LLC VSSD(P1) UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 VDDD(P2) Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 VSSD(P2) VDDD(C3) A1/SNRES A0/SNDA SDA VSSD(C3) SCL/SNCL VSSD(C4) XIN XOUT PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O I I O O I I I O O O O O I O O O O O O O O I O O O O O O O O I I I I I I I I I O analog ground for to band gap pin to be used for external decoupling of band gap external bias resistor connection for band gap analog supply for band gap digital supply 1 for CLK2 related peripherals output clock (CLK2 frequency is 2 x CLK1 frequency) field identification output pulse vertical synchronization output horizontal reference output for YUV-port clock/pixel qualifier output for YUV-port line-locked system clock output digital ground 1 for CLK2 related peripherals multiplex chrominance UV bit 7 (MSB) multiplex chrominance UV bit 6 multiplex chrominance UV bit 5 multiplex chrominance UV bit 4 multiplex chrominance UV bit 3 multiplex chrominance UV bit 2 multiplex chrominance UV bit 1 multiplex chrominance UV bit 0 (LSB) digital supply for CLK2 related peripherals luminance Y or multiplexed YUV bit 7 (MSB) luminance Y or multiplexed YUV bit 6 luminance Y or multiplexed YUV bit 5 luminance Y or multiplexed YUV bit 4 luminance Y or multiplexed YUV bit 3 luminance Y or multiplexed YUV bit 2 luminance Y or multiplexed YUV bit 1 luminance Y or multiplexed YUV bit 0 (LSB) digital ground 2 for to CLK2 related peripherals digital supply 3 for digital core and CLK1 related peripherals I2C-bus address select pin A1 or SNERT reset input I2C-bus address select pin A0 or SNERT data input/output I2C-bus data input/output digital ground 3 for digital core and CLK1 related peripherals I2C-bus clock/SNERT clock input digital ground 4 for digital core and CLK1 related peripherals input crystal oscillator for subcarrier lock applications output crystal oscillator for subcarrier lock applications DESCRIPTION analog supply for analog core of triple DAC
SAA8110G
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
77 SCL/SNCL
72 VDDD(C3)
62 VDDD(P2)
78 VSSD(C4)
76 VSSD(C3)
71 VSSD(P2)
74 A0/SNDA
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73 A1/SNRES
80 XOUT
75 SDA
VDDD(C1) CLK1 VSYNCIN HSYNCIN FIIN VSSD(C1) CCD9 CCD8 CCD7
61 UV0 60 UV1 59 UV2 58 UV3 57 UV4 56 UV5 55 UV6 54 UV7 53 VSSD(P1) 52 LLC 51 CREF/PXQ 50 HREF 49 VSYNCOUT 48 FIOUT 47 CLK2 46 VDDD(P1) 45 VDDA(BG) 44 RBIAS 43 DECOUPL 42 VSSA(BG) 41 VDDA(DC) VDDA(O1) 40
79 XIN
70 Y0
69 Y1
68 Y2
67 Y3
66 Y4
65 Y5
64 Y6 OUT2 37
1 2 3 4 5 6 7 8 9
CCD6 10
SAA8110G
CCD5 11 CCD4 12 CCD3 13 CCD2 14 CCD1 15 CCD0 16 VSSD(C2) 17 SCLK 18 VSSA(CD) 19 CDACOUT 20 CDACRBIAS 21 VDDA(CD) 22 SDATA 23 STROBE 24 SMP 25 P0 26 P1 27 SIS 28 VDDD(C2) 29 RESET 30 T2 31 T1 32 T0 33 VSSA(OB) 34 OUT3 35 VDDA(O3) 36 VDDA(O2) 38 OUT1 39
63 Y7
MGK151
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
FUNCTIONAL DESCRIPTION Black offset preprocessing The input data is clamped within the optical black pixel area of the CCD. The size of the digital clamp window is 16 pixels by 128 lines (i.e. TDA8786). It is possible to differentiate black levels for odd/even lines, pixels and fields. This comes in addition to the analog preprocessing clamp which is active on the clamp pulse generated by the external timing circuit. The analog clamp is included in the TDA8786. RGB separation PAL/NTSC sensors generate interlaced data adding offset in the complementary colour pixels. The RGB separation block with its two line memories generates the three components Y, 2R - G, and 2B - G for each input data corresponding to a pixel value of the CCD. Then the triplet R, G, B is derived. This block also delivers some contour and white clip information. RGB processing
SAA8110G
The RGB processing includes several features: * Colour space matrix depending on CCD type to be suitable with different sensor colour filters * Gain correction for R and B signals for white balance control * Black offset * Adjustable knee * Adjustable gamma function. The knee function is applied to all three RGB signals. Its shape is continuously adjustable by changing the slope and the knee offset point. To compensate for the non-linear response of display devices, a gamma correction is applied to R, G and B signals. It may be adjustable from linear to a 0.35 power coefficient.
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LINE MEMORY
R G
LINE MEMORY 10 CCD inputs
RGB COLOUR SEPARATION
B white clip vertical contour
MGK153
Fig.3 RGB separation diagram.
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Rgain R
x
Rblack
+ + +
R 3x KNEE 3x GAMMA G
Gblack G COLOUR MATRIX Bgain B
x
Bblack B
MGK154
Fig.4 RGB processing.
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
RGB-to-YUV block After RGB processing, the channels are separated in a luminance and two colour difference path: Y = 0.299 R + 0.597 G + 0.114 B, U = 0.49 (B - Y) and V = 0.88 (R - Y) . It also contains two down-sampling filters for U and V signals. Y-processing The luminance component includes several features:
SAA8110G
* Contour correction allowing an increase of the luminance transitions for a sharper picture * Black stretch function for contrast enhancement in dark scenes * False colour detector used by the UV-processing block to enable the colour killer * Filters and noise reduction by coring (only in the high frequency part of the signal).
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9 R G B CONVERSION MATRIX
Y (0 to 511)
DOWNSAMPLING & MUX
8
UV (-128 to 127)
MGK155
Fig.5 RGB-to-YUV conversion.
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vertical contour (-512 to 511) (from RGB-separation)
10 CONTOUR PROCESSING AND FALSE COLOUR DETECTION false colour
Y (0, 0.5 to 255.5)
9 BLACK STRETCH
+
NOISE REDUCTION
8 Y
MGK156
Fig.6 Y processing.
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
handbook, full pagewidth
UV (-127 to 128)
8
NOISE REDUCTION
FALSE COLOUR CORRECTION
UV GAIN CONTROL
8
UV (-127 to 128)
false colour (from Y-processing)
white clip (from RGB-separation)
MGK157
Fig.7 UV-processing.
UV-processing The chrominance component includes several features: * Noise reduction for high frequencies * False colour correction: a colour killer cuts the false colour components in the UV signals * UV-gain control used to set the correct UV levels for PAL/NTSC encoding. As the colour filter saturation levels may be different in the CCD, the white clip is used in the UV-processing to suppress colour errors in case of high exposure. Digital output formatter This block contains several features: * Generation of a synchronous clock LLC (twice the clock frequency) * Generation of three synchronization signals (HREF, CREF and VS) * Synchronization of the output data to the output clock LLC * Generation of a CIF/QCIF output format for several type of sensors (see Table 1) * Selection of the required digital output format (8-bit multiplexed YUV standard D1/CCIR 656, including the generator of SAV/EAV codes or 16-bit multiplexed YUV 4 : 2 : 2 standard DTV2/CCIR601). Note that the D1 frequency data rate is twice the DTV2 frequency data rate.
Moreover, using a high resolution PAL and NTSC CCDs, it is possible to generate the following formats by means of cutting or down-sampling. * CIF 352 x 288 at 25 frame/second and CIF 352 x 240 at 30 frame/second * QCIF 176 x 144 at 25 frame/second and QCIF 176 x 120 at 30 frame/second. Table 1 CIF/QCIF output format for different sensor types OUTPUT FORMAT CIF CIF QCIF QCIF QCIF CIF QCIF QCIF `full screen' `zoom-by-2' `full screen' `zoom-by-2' `zoom-by-4' `full screen' `zoom-by-2'
INPUT FORMAT PAL/NTSC-sensor
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
19
20
21
22
23
HSYNCIN VSYNCIN FIIN VSYNCOUT FIOUT CSYNC
BLANK
BURST
MGK159
Fig.8 Vertical timing NTSC odd field.
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HSYNCIN VSYNCIN FIIN VSYNCOUT FIOUT CSYNC
BLANK
BURST
MGK160
Fig.9 Vertical timing NTSC even field.
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
20
2 1 22
23
24
25
HSYNCIN VSYNCIN FIIN VSYNCOUT FIOUT CSYNC
BLANK
-
BURST(1)
+ even frame
odd frame
odd frame even frame
+ + -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
+
MGK161
(1) +: burst phase = +135. -: burst phase = -135.
Fig.10 Vertical timing PAL odd field.
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332 333 334 335 336 337
HSYNCIN VSYNCIN FIIN VSYNCOUT FIOUT CSYNC
BLANK
-
BURST(1)
+ - +
odd frame even frame
+
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
- +
+ -
+
MGK162
(1) +: burst phase = +135. -: burst phase = -135.
Fig.11 Vertical timing PAL even field.
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
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0
NPIX
HSYNCIN
BLANK
BURST
HREF
MGK163
Fig.12 Horizontal timing for non-CIF processing.
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SAA8110G (OUTPUTS CLOCKED AT CLK2)
Y(UV)7 to Y(UV)0 LLC PXQ HREF VSYNCOUT
YUV
HOST
Y(UV)
FF
00
00
SAV
U0
Y0
V0
Y2
U4
Y4
V4
Y6
LLC
PXQ
HREF sample moment
MGK164
Fig.13 8-bits multiplexed format (D1, CCIR656); example: CIF down-sampling.
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
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SAA8110G (OUTPUTS CLOCKED AT CLK2)
Y(UV)7 to Y(UV)0 LLC PXQ HREF VSYNCOUT
YUV
HOST
YUV
FF
00
00
SAV
U0
Y0
V0
Y1
U2
Y2
V2
UN-1 YN-1
FF
00
00
EAV
LLC
PXQ
HREF sample moment
MGK165
Fig.14 8-bits multiplexed format (D1, CCIR656); SAV/EAV included.
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Y7 to Y0 Y(UV) UV7 to UV0 UV SAA8110G (OUTPUTS CLOCKED AT CLK2) HOST
LLC CREF HREF VSYNCOUT FIOUT
Y(UV)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
UV
U0
V0
U2
V2
U4
V4
U6
LLC
CREF
HREF sample moment
MGK166
Fig.15 16-bits multiplexed format (DTV2, CCIR601).
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Analog output preprocessing This block contains several features: * Delay compensation for the luminance signal * Up-sampling of the UV signal * PAL/NTSC encoding * YUV to RGB conversion * Selection of the required analog output format (RGB, YUV, YC or CVBS). The analog outputs are given by three voltage DACs in RGB or YUV or CVBS or YC format. Channels Y and G include the sync information. Over-sampling at twice fclk is made so that external filtering becomes easier. It is also possible to have an adjustment of the subcarrier via the serial interface. When CVBS output is used, chrominance range is halved compared to luminance. Measurement engine The measurement engine performs measurements on some selectable internal signals on frame/field basis and prepares data for auto exposure, auto focus and auto white balance processing. It uses an internal RAM work-space for its control and data handling operations. The contents of the work-space can be accessed via the serial interface. Vertical/horizontal reference and window timing and control The SAA8110G uses two vertical and horizontal synchronization input signals (VSYNCIN and HSYNCIN) to derive internal vertical and horizontal reference signals. Besides a Field Identification input (FIIN) signal is required. The timing of the vertical and horizontal input signals should be such that: 1. The pixel frequency (CLK1) must be line-locked to the line frequency of HSYNCIN: the number of clock periods between two HSYNCIN pulses must be a fixed integer number. The HSYNCIN should be at least one clock period active HIGH. 2. The VSYNCIN signal indicates the start of a field (or frame in case of progressive scanning); this signal is also required for non-interlaced applications. The VSYNCIN should be at least one clock period HIGH. 3. The FIIN pulse indicates the phase of the field in case of interlaced applications (FIIN = 0 means odd field). Serial interface
SAA8110G
The serial interface can either be an I2C-bus or a 80C51 UART (SNERT) (selectable with the SIS pin). Via the serial interface the external microcontroller can control the internal settings of the SAA8110G and read/write from/to the internal RAM work-space linked to the measurement engine (see list of parameter settings in Chapter "Programming"). Some of the registers are double-buffered to prevent that the change of control data becomes visible on the output display. Miscellaneous functions A three wire bus is used to send 10-bit settings from a microcontroller to the TDA8786 via the SAA8110G registers.The SAA8110G supplies picture parameters and needs some configuration parameters. Those values are contained in registers and are updated during every vertical synchronization pulse. Mode control This block controls the operation mode of the SAA8110G. As described in Table 2, four modes may be selected: depending on power reduction and I2C-bus timing. Power dissipation management The power dissipation of the SAA8110G will depend on the required activity for a certain application. It is possible to switch off via the serial interface unconcerned parts for a given application. When an analog output is not used, the power voltage pin of the DAC can be connected to ground to limit the power consumption. Clock configurations Following conditions must be fulfilled: * CLK1 should be generated as divide-by-two from CLK2 * The RESET pin should not go LOW before CLK1 and CLK2 are both HIGH or LOW. Table 2 T2 0 0 0 0 T1 0 0 1 1 SAA8110G mode control T0 0 1 0 1 MODE application mode POWER REDUCTION on on off off to(h) I2C-BUS short long short long
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Table 3 Sensor and output formats covered by the SAA8110G CCD-formats RESOLUTION PIXEL FREQUENCY (MHz)
SAA8110G
OUTPUT FORMATS DIGITAL ANALOG DTV2/D1 CIF
STANDARD CIF CIF NTSC high resolution PAL high resolution
FRAME SCANNING AND FREQUENCY (Hz) non-interlaced non-interlaced non-interlaced interlaced non-interlaced interlaced 60 50 60.054 29.997 50 25 60 30 50 25
ACTIVE H/V 352/243 352/288 768/243 768/494 752/288 752/582 512/243 512/492 512/288 512/582
TOTAL H/V 429/262 432/312 910/262 910/525 908/312 908/625 606/262 606/525 618/312 618/625 9.65625 6.75 6.75 14.3181 14.1875 9.53495
no no yes yes yes yes
yes yes yes yes no no
yes yes yes yes yes yes
NTSC non-interlaced medium resolution interlaced PAL non-interlaced medium resolution interlaced
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VDDD VDDA VDDD-DDA VI VO Ptot Tstg Tj HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 50 UNIT K/W digital supply voltage analog supply voltage supply voltage difference between the digital and the analog supply voltages input voltage output voltage total allowed power dissipation at Tamb = 75 C storage temperature junction temperature PARAMETER MIN. -0.3 -0.3 -0.1 -0.3 -0.3 - -55 - MAX. +7.0 +7.0 +0.1 VDD + 0.3 VDD + 0.3 1 +150 125 V V V V V W C C UNIT
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
CHARACTERISTICS SYMBOL VDACs specification OUTPUTS PINS OUT1 TO OUT3 (IN CASE OF SCALE FACTOR = 1) Vo Voffset INPUTS Rbias Rext Cdecoup RES NLdiff NLint THD60 S/N bias resistor external anti-reflection resistor decoupling capacitor note 2 note 3 note 2 note 3 TRANSFER FUNCTION resolution differential non-linearity integral non-linearity total harmonic distortion at 60% of full-scale signal-to-noise ratio fclk = 30 MHz, fi = 1 MHz, VDDA = 5 V fclk = 30 MHz, fo = 1 MHz, VDDA = 5 V - - - - - 9 - - 55 45 14 44 - - 10 15 47 21 70.6 - output voltage (see note 1) amplitude offset voltage between DACs code 0 code 511 0 1.3 -60 0.2 1.5 PARAMETER CONDITIONS MIN. TYP.
SAA8110G
MAX.
UNIT
0.3 1.6 +60
V V mV
16 50 - - 100 - 1.5 1.5 45 38
k k nF
bit LSB LSB dB dB
APPLICATION1: PAL/NTSC HIGH RESOLUTION VDD1 VDD2 CR fclk Ba VDD1 VDD2 fclk Ba tPD tst(10-90) tst(LSB) supply voltage supply voltage conversion rate clock frequency analog bandwidth 4.5 3.0 - - - 4.5 3.0 - - to 50% value 10% to 90% full-scale - - - 5.0 3.3 28.6 28.6 7.6 5.5 3.6 - - - 5.5 3.6 - - 13 11 30 V V MHz MHz MHz
APPLICATION 2: PAL/NTSC MEDIUM RESOLUTION supply voltage supply voltage clock frequency analog bandwidth 5.0 3.3 19 6.5 V V MHz MHz
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP (see Fig.16) propagation delay time settling time setting time (to 1 LSB) 9 9 25 ns ns ns
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA8110G
MAX.
UNIT
CDAC specification (VDD = 5 V) Lint Ldiff Vo(CDAC) integral linearity differential linearity output voltage at pin CDAC code 0 code 61, VDDA = 5 V code 61, VDDA = 3.3 V Ro(CDAC) fclk RL CL tPD tst(10-90) tst(LSB) tsu(i)(D)1 tsu(i)(D)2 th(i)(CCD) th(i)(D) th(o)(D) td(o)(D) th(o)(D) td(o)(D) clk Notes 1. When CVBS output is used the chrominance range is halved compared to luminance. 2. Monitor load of 75 with Rext = 21 and Rbias = 15 k at 3.3 V application. 3. Monitor load of 75 with Rext = 70.6 and Rbias = 47 k at 5.0 V application. output resistance at pin CDAC clock frequency load resistance load capacitance propagation delay time settling time setting time to 50% value (see Fig.17), VDDA = 5 V 10% to 90% full-scale (see Fig.16) to 1 LSB (see Fig.16) - - - -4.6 3 - - - - - - - 0 0 -1 VSYNCIN, HSYNCIN, FIIN 0 - - - - 40 - - 10 4.95 3.25 13 28.6 10 - - 9 25 1
1 2
LSB LSB mV V V MHz k pF ns ns ns
300 - - - - - 10 104 - - 5 2 +1 3
INPUTS RELATED TO CLK1: CCD0 TO CCD9, VSYNCIN, HSYNCIN, FIIN data input set-up time CCD inputs, HSYNCIN, VSYNCIN, FIIN data input set-up time SNRES and SNDA data hold time CCD inputs data input hold time 3 1 - 1 ns ns ns ns
OUTPUTS RELATED TO CLK2: Y7 TO Y0, UV7 TO UV0, CREF, HREF, VSYNCOUT, FIOUT AND LLC data output hold time data output delay time 8 25 22 31 ns ns
OUTPUTS RELATED TO CLK1: SDATA, STROBE, SMP, P0, P1 AND SCLK data output hold time data output delay time clock duty cycle 13 15 - 21 24 60 ns ns %
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
handbook, full pagewidth
CLK2 code FS input code (example of a full-scale input data transmission) (code FS) 1 LSB 10% 50% 90% (code 0) 1 LSB code 0
tst(10-90) tPD tst(LSB)
MGK167
Fig.16 Switching characteristics.
handbook, full pagewidth
CLK1
tsu DATA IN tPD
th(i)(D)
DATA OUT
MGK168
Fig.17 Data input/output timing.
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
PROGRAMMING Overview available write ADDRESS 0 1 2 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 34 35 36 37 38 SYMBOL CONTROL0 CONTROL1 CONTROL2 OB_STARTL_F0 OB_STARTL_F1 OB_STARTP OB_PE_F0 OB_PO_F0 OB_PE_F1 OB_PO_F1 OB_OFFSET_LE OB_OFFSET_LO MOSAIC_SEP_S1 MOSAIC_SEP_S2 MOSAIC_SEP_S3 MOSAIC_SEP_S4 WHITE_CLIP_THR COL_MAT_P11 COL_MAT_P12 COL_MAT_P13 COL_MAT_P21 COL_MAT_P22 COL_MAT_P23 COL_MAT_P31 COL_MAT_P32 COL_MAT_P33 COL_MAT_RGAIN COL_MAT_BGAIN BLACK_LEVEL_R BLACK_LEVEL_G BLACK_LEVEL_B GAMMA_BALANCE FUNCTION miscellaneous; see Table 4 miscellaneous; see Table 5(1) miscellaneous; see Table 6 first line optical black window in field 0 first line optical black window in field 1/frame first pixel optical black window fixed optical black level for even pixel in field 0 fixed optical black level for odd pixel in field 0 fixed optical black level for even pixel in field 1/frame fixed optical black level for odd pixel in field 1/frame optical black offset for even line optical black offset for odd line multiplication-factor for Yn at even line and even pixel multiplication-factor for Yn at even line and odd pixel multiplication-factor for Yn at odd line and even pixel multiplication-factor for Yn at odd line and odd pixel threshold for white clip colour matrix coefficient p11 colour matrix coefficient p12 colour matrix coefficient p13 colour matrix coefficient p21 colour matrix coefficient p22 colour matrix coefficient p23 colour matrix coefficient p31 colour matrix coefficient p32 colour matrix coefficient p33 colour matrix R-gain colour matrix B-gain factor(1) factor(1) FORMAT byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte (LS)(1) 6 bits
SAA8110G
RANGE/VALUE n.a. n.a. n.a. 0 to 255 0 to 255 0 to 255 0 0 0 0 0 0 0 to 255 0 to 255 0 to 255 0 to 255 768 to 1023 -128 to 127 -128 to 127 -128 to 127 -128 to 127 -128 to 127 -128 to 127 -128 to 127 -128 to 127 -128 to 127 0 to 255 0 to 255 -128 to 127 -128 to 127 -128 to 127 0 to 255 0 to 63
fixed R-black level offset(1) fixed G-black level offset(1) fixed B-black level offset(1)
RGB_KNEE_OFFSET offset for RGB-knee(1) gamma multiplication factor
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
ADDRESS 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1997 Jun 13 SYMBOL NPIX_LSB NPIX_MSB FPIX_ACT LPIX_ACT_LSB FLINE_ACT_F0 LLINE_ACT_F0_LSB FLINE_ACT_F1_LSB LLINE_ACT_F1_LSB ACT_LINES_MSB CTR_UPD_LINE KCOMB VCGAIN CLDLEV HCHGAIN HCLGAIN CNCLEV CONGAIN FCDLEV YNCLEV YGAIN YCMPDEL UVNCLEV UGAIN VGAIN DTO_FREQ_LSB DTO_FREQ_ISB DTO_FREQ_MSB PHASESHIFT BURST_LEVEL A B C D E F HIGHLIGHTTHR FUNCTION number of pixels on a line number of pixels on a line number of first active pixel on a line number of last active pixel on a line number of first active line in field 0 number of last active line in field 0 number of first active line in field 1/frame number of last active line in field 1/frame MSBs of active line numbers number of line for double buffered update control registers vertical contour comb filter coefficient (MS) vertical contour gain (LS) contour level dependancy level(1) horizontal contour band pass filter high gain (MS) horizontal contour band pass filter low gain (LS) contour noise coring level(1) contour gain factor false colour detect level Y (luminance) noise coring level Y (luminance) gain factor(1) Y (luminance) compensation delay UV (chrominance) noise coring level U(B - Y) gain V(R - Y) gain factor(1) factor(1) FORMAT byte 2 bits byte byte byte byte byte byte byte byte 3 bits 4 bits byte 4 bits 4 bits 6 bits byte byte byte byte 4 bits byte byte byte byte byte byte byte byte byte byte byte byte byte 6 bits byte 6 bits byte byte
SAA8110G
RANGE/VALUE 0 to 255 0 to 3 0 to 255 0 to 255 0 to 255 0 to 255 0 to 255 0 to 255 see Table 7 0 to 255 0 to 7 0 to 15 0 to 255 0 to 15 0 to 15 0 to 63 0 to 63 0 to 255 0 to 127 0 -3 to 4 see Table 8 0 to 255 0 0 0 to 255 0 to 255 0 to 255 0 to 255 0 to 255 -98 0 to 255 -104 -68 126 63 63 0 0 60
DTO frequency (MSB)(1) DTO frequency(1) DTO frequency (LSB)(1) PHASE_SHIFT colour subcarrier BURST_LEVEL colour burst AWB_A (ME) pole_thresh #A (DPD) AWB_B (ME); pole_thresh #B (DPD) AWB_C (ME); pole_thresh #A (DPD) AWB_D (ME); pole_thresh #B (DPD) AWB_E (ME) pole_thresh #A (DPD) AWB_F (ME) pole_thresh #B (DPD) highlight-threshold (ME); pole_thresh #A(DPD) 21
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
ADDRESS 73 SYMBOL ME_RESSCALE FUNCTION ME_sync + ME_Resultscale (ME) pole_thresh #B (DPD) 74 78 79 82 83 84 85 86 87 88 89 90 91 92 93 94 126 127 Note 1. Double buffered write register. MWHVGRID WHITECLIP AUTO_BLACK DOP_CNTRL0 DOP_CNTRL1 CIF_WSTRT CIF_WSTRT PRE_SI_LSB PRE_SI_MSB SMP_CNTRL PRE_CNTRL DIG_SETUP BLANKLEV BL-SETUP AOF_CNTRL PRE_PROC_DEL RAMWRPTR RAMWRDATA measurement horizontal and vertical grid white clip limiter level for analog outputs auto black attack slope control digital output processing control digital output processing control(1) CIF-window start pixel (LSBs) CIF-window start line (LSBs) control data for analog preprocessing control data/address for analog preprocessing control for switched mode power supply preprocessing/timing control set-up in digital output blanking level in analog output set-up level in analog output analog output format control(1) control compensation delay W.I.L preprocessing write pointer for RAM work-space write data for RAM work-space FORMAT 4 bits byte 6 bits byte 2 bits byte byte byte byte byte 5 bits byte byte byte byte byte byte 4 bits byte byte
SAA8110G
RANGE/VALUE 0, 1 see Table 9 0 to 255 see Table 10 256 + (0 to 255) see Table 20 see Table 11 see Table 12 0 to 255 0 to 255 0 to 255 see Table 13 0 see Table 14 0.255 0 to 255 0 to 255 see Table 15 0 to 15 0 to 223 0 to 255
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Register details Table 4 CONTROL0 NAME AUTO_OPT_BLACK SENS_VGA MOSAIC_FIL_TYPE PIX_PHASE LINE_PHASE FIELD_PHASE FUNCTION Auto Optical Black ON/OFF
SAA8110G
NAME.BITNR CONTROL0.0 CONTROL0.1 CONTROL0.2 CONTROL0.3 CONTROL0.4 CONTROL0.5 Table 5 CONTROL1
RGB-bayer/complementary mosaic colour filter complementary mosaic colour filter toggle phase for pixel in colour separation toggle phase for line in colour separation toggle phase for field in colour separation
NAME.BITNR CONTROL1.2 CONTROL1.3 CONTROL1.4 CONTROL1.5 CONTROL1.6 CONTROL1.7 Note 1. Double buffered write register. Table 6 CONTROL2
NAME RGB_KNEE_K RGB_KNEE_K MED_RES PAL_NTSC BSSCALE BSSCALE
FUNCTION compression factor for RGB-knee (see Table 16)(1) compression factor for RGB-knee (see Table 16)(1) medium resolution for PAL/NTSC encoder choose between PAL/NTSC black stretch scaling factor (see Table 17)(1) black stretch scaling factor (see Table 17)(1)
NAME.BITNR CONTROL2.0 CONTROL2.1 CONTROL2.2 CONTROL2.3 CONTROL2.4 CONTROL2.5 CONTROL2.6 CONTROL2.7 Note 1. Double buffered write register. Table 7 ACT_LINES_MSB NAME.BITNR NI
NAME FCC_FILTER+ DTOMWL_LSB DTOMWL_MSB WH_CL_MAP WH_CL_MAP FC_MAP FC_MAP
FUNCTION false colour low-pass filter ON/OFF non-interlaced/interlaced DTO measurement window length(1) DTO measurement window length(1) white clip mapping on UV-grid (see Table 18) white clip mapping on UV-grid (see Table 18) false colour mapping on UV-grid (see Table 19) false colour mapping on UV-grid (see Table 19)
FUNCTION bits 8 and 9 for last active pixel number on a line bits 8 and 9 for last active line number in field 0 bits 8 and 9 for first active line number in field 1/frame bits 8 and 9 for last active line number in field 1/frame
ACT_LINES_MSB.0 and ACT_LINES_MSB.1 ACT_LINES_MSB.2 and ACT_LINES_MSB.3 ACT_LINES_MSB.4 and ACT_LINES_MSB.5 ACT_LINES_MSB.6 and ACT_LINES_MSB.7
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Table 8 YCMPDEL CONTENT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 9 MECNTRL NAME.BITNR MECNRTL.0, MECNRTL.1, MECNRTL.2 MECNRTL.3 Table 10 MWHVGRID NAME.BITNR MWHVGRID.0, MWHVGRID.1, MWHVGRID.2 and MWHVGRID.3 MWHVGRID.4 and MWHVGRID.5 Table 11 DOP_CNTRL0 NAME.BITNR DOP_CNTRL0.0 and DOP_CNTRL0.1 DOP_CNTRL0.2 and DOP_CNTRL0.3 DOP_CNTRL0.4 and DOP_CNTRL0.5 DOP_CNTRL0.6 DOP_CNTRL0.7 FUNCTION FUNCTION horizontal ME-window pixel size selection vertical ME-window pixel size selection FUNCTION ME_Resultscaler selection (0, 2, 4, 8, 16, 32) FUNCTION (1 + 4 x B3 + B2 + 2 x B1 + 1 x B0) x td 1td 2td 3td 4td 5td 6td 7td 8td 5td 6td 7td 8td 9td 10td 11td 12td
SAA8110G
DEFAULT 1 0
ME_Sync (synchronize field/frame toggle of measurement engine)
DEFAULT 4 4
horizontal CIF-processing control bits HCIF.0 and HCIF.1 (see Table 21) vertical CIF-processing control bits VCIF.0 and VCIF.1 (see Table 22) temporal CIF-processing control bits TCIF.0 and TCIF.1 (see Table 23) CIF-processing enabled/disabled (by-pass) CIF-format/QCIF format
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Table 12 DOP_CNTRL1 NAME.BITNR DOP_CNTRL1.0 and DOP_CNTRL1.1 DOP_CNTRL1.2 and DOP_CNTRL1,3 DOP_CNTRL1.4 DOP_CNTRL1.5 DOP_CNTRL1.6 DOP_CNTRL1.7 Table 13 PRE_SI_MSB NAME.BITNR PRE_SI_MSB.0 and PRE_SI_MSB.1 PRE_SI_MSB.2 to PRE_SI_MSB.4 Table 14 PRE_CNTRL NAME.BITNR PRE_CNTRL.0 to PRE_CNTRL.5 PRE_CNTRL.6 and PRE_CNTRL.7 Table 15 AOF_CNTRL NAME.BITNR AOF_CNTRL.0 and AOF_CNTRL.1 AOF_CNTRL.2 and AOF_CNTRL.3 AOF_CNTRL.4 and AOF_CNTRL.5 AOF_CNTRL.6 AOF_CNTRL.7 Table 16 Knee compression factors W 1.n COMPRESSION FACTOR n=3 0 0 1 1 n=2 0 1 0 1
1 8 1 4 3 8 1 2
SAA8110G
FUNCTION horizontal pixel start MSBs for CIF-window vertical line start MSBs for CIF-window PXQ-output/CREF-output CIF-sensor applied/non CIF-sensor applied d1/d2 output format DOP-processing active/disabled
DEFAULT - - - - - 1
FUNCTION control data bits d8 and d9 control address bits a0 to a2
FUNCTION control DAC-data bits 0 to 5 static control outputs P0 and P1
FUNCTION analog output format selection (see Table 24) scale factor #1 for GY-multiplex (see Table 25) scale factor #2 for BU-, C- and RV-multiplex (see Table 26) analog output processing active/disabled triple DAC output range control large/small Table 17 Black stretch scaling factors W 1.n
DEFAULT 1 - - 1 -
SCALING FACTOR n=7 0 0 1 1 n=6 0 1 0 1 0
1 4 1 2 3 4
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
Table 18 White-clip detection spreading W 2.n SPREADING FILTER n=5 0 0 1 n=4 0 1 X [0 0 1 0 0] [0 1 1 1 0] [1 1 1 1 1] n=5 0 0 1 1 Table 19 False colour detection spreading W 2.n SPREADING FILTER n=7 0 0 1 n=6 0 1 X [0 0 1 0 0] [0 1 1 1 0] [1 1 1 1 1] n=1 0 0 1 Table 20 Auto black attack slope control W 79.n SLOPE FACTOR n=7 0 0 1 1 n=6 0 1 0 1
1 4 1 8 1 16 1 32
SAA8110G
Table 23 TCIF-control W 82.n PROCESSING n=4 0 1 0 1 one-to-one copy down-sample by 2 down-sample by 4 down-sample by 8
Table 24 Analog output format selection W 93.n FORMAT n=0 0 1 0 1 RGB YUV YC CVBS
1
Table 25 Scale #1 selection W 93.n SCALE FACTOR n=3 0 1 1 n=2 X 0 1 1 2
3 2
Table 21 HCIF-control W 82.n SLOPE FACTOR n=1 0 0 1 n=0 0 1 X down-sample by 4 down-sample by 2 one-to-one copy n=5 0 1 1 Table 22 VCIF-control W 82.n PROCESSING n=3 0 0 1 1 n=2 0 1 0 1 down-sample by 4 down-sample by 2 one-to-one copy up-sample by 2 Table 26 Scale #2 selection W 93.n SCALE FACTOR n=4 X 0 1 1 2
3 2
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
APPLICATION INFORMATION
SAA8110G
TDA8786 and SAA8110G can be used with Sharp CCDs. TDA8786A and SAA8110G can be used with Sony CCDs. Table 27 gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110G. This overview is not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones. Table 27 Possible components for the application of Figs 18 and 19. NTSC CCD TYPE SONY CCDs COMPONENT TYPE CCD V-driver timing generator SHARP CCDs CCD V-driver timing generator Notes to the application diagram * In the configuration of Figs 18 and 19, the microcontroller reads and writes data from/to the DSP using the SNERT-bus (UART-mode 0). Optional external control is available through the I2C-bus. * Free I/O pins of the microcontroller can be used to control PGG, or for other purposes. * 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD. * A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office. CXD1257AR LZ95G55 ICX056AK LZ95G71 ICX068AK CXD1265R MEDIUM RESOLUTION LZ2313H5 HIGH RESOLUTION LZ2353A MEDIUM RESOLUTION LZ2323H5 LR36683N LZ95G55 ICX057AK CXD1257AR LZ95G71 ICX069AK CXD1265R PAL HIGH RESOLUTION LZ2363
CXD1250MN; CXD1267N
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
handbook, full pagewidth
P0 P1 CDACOUT CLK1 CLK2 CDSPULSE1 CDSPULSE2 digital ground analog ground
P0 (optional, PPG setting) P1 (optional, PPG settings) CDACOUT (optional, can be used for frequency tuning) CLK1 (to ADC and DSP) CLK2 (to DSP, CLK2 = 2 x CLK1) CDSPULSE1 CDSPULSE2 CLAMPCDS (CLAMP CDS, OPB, ADC can be the same) CLAMPOPB CLAMPADC PreBlank (optional) HD (to DSP and C) VD (to DSP and C) FI (to DSP and C) CLK1 CLAMPCDS CDSPULSE1 CDSPULSE2 100 nF VDDA1 100 nF 1 F OEN (optional) (from microcontroller) VDDD CLPCDS 100 nF VCCO OE
VERTICAL DRIVER (PPG)
CLAMPCDS CLAMPOPB CLAMPADC PreBlank Horizontal Drive Vertical Drive Field Id
V4
V3
V2
V1
H1
H2
Electrical Reset Shutter Pulse
VERTICAL DRIVER BUFFER Reset CCDout OFD level (optional) CLAMPOPB PreBlank
VDDA1
V4 V3 V2 V1
H1
H2
Shutter
CCD
CLPOPB -xxV +xxV 100 nF SMP_CLK (from DSP) VDDA1 PBK OFDOUT AMPOUT 100 nF AMPOUT AGND1 VCCA1 AGCOUT PBIN 220 nF PBOUT ADCIN CLPADC Vref 220 nF 10 k BC848C VD (from PPG) 10 F VDDD P1.0 P1.1 P1.2 OEN (optional) (to ADC) P1.3 P1.4 P1.5 VDDD 4.7 F JB JB JB JB VDDD P1.6/SCL P1.7/SDA RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VDD P0.0/AD0 CLAMPADC (from PPG) 1 nF VDDD
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DACOUT AGND2 VCCA2 DEC1 STGE SDATA SCLK SEN VRB VRT STBY VCCD1 36 35 34
DGND2 VCCD2
AGND3
VCCA3
CDSP2
CDSP1
CLK
IN2
IN1
OGND1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 A B C D E F G H I J K
SWITCH MODE POWER SUPPLIES (optional)
ANALOG TO DIGITAL INTERFACE
33 32 31
5V 5V 5V
VDDA1 VDDA2 VDDA3
VDDD
TDA8786G or TDA8786AG
30 29 28 27 26 25
100 nF VDDD
10 k
2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22
44 43
VDDA1 SDA SCL
P0.1/AD1 MICRO42 CONTROLLER P0.2/AD2 41 40 39 38 37 36 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 4.7 k
EPROM A2 6 PCF8598 3 NC VDDD PTC 7 PCF8594 2 4.7 VDD WP k 8 PCF8582 1
100 nF
5
4
VSS
100 nF
L 1 nF 1 nF 2.2 nF 200 nF M
VDDD VDDD
+5 V
GND
SCL
SDA
83C54/ 35 EA VDDD 83C654 ALE (OM-XXX) 33 PSEN
32 31 30 29 28 27 26 25 24 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
MGK393
4
3
2
1 A0/SNDA SCL/SNCL HD (opt.) FIIN A1/SNRES 18 pF 12 MHz
RESET_DSP (to DSP)
18 pF
Fig.18 SAA8110G system configuration for camera application (continued in Fig.19).
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SAA8110G
handbook, full pagewidth
26
25
22 A1/SNRES A0/SNDA SDA SCL/SNCL VDDD 100 nF VDDD optional 100 nF
A1/SNRES VDDD(C3) VSSD(P2) SCL/SNCL VSSD(C3) Y7 VDDD(P2) XOUT XIN VSSD(C4) SDA A0/SNDA
DIGITAL OUTPUT CONNECTOR
24
23 21 19 17 15 13 11 9 7 5 3 1 VDDD
20 18 16 14 12 10 8 6 4 VDDD 2
Y4
Y0
Y2
Y5
Y1
100 nF V DDD(C1) CLK1 VD HD FI CLK1 VSYNCIN HSYNCIN FIIN VSSD(C1) CCD9 CCD8 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 VSSD(C2)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 60 59 58 57 56
Y3
Y6
VDDD
UV0
UV1 UV2 UV3 UV4 UV5 UV6 UV7 VSSD(P1) LLC CREF/PXQ HREF VSYNCOUT FIOUT CLK2 VDDD(P1) VDDA(BG) RBIAS CLK2 (from PPG) VDDD 47 k VDDA3 100 nF
DIGITAL SIGNAL PROCESSOR
55 54 53 52 51
A B C D E F G H I J K
SAA8110G
50 49 48 47 46 45 44 43
VDDA(CD)
VDDD(C2)
P0
P1
OUT3 VDDA(O3)
OUT2 VDDA(O2)
CDACRBIAS
T0 VSSA(OB)
OUT1 VDDA(O1)
SDATA
STROBE
SMP
SIS
RESET
T2
T1
100 nF DECOUPL VSSA(BG) 100 nF 19 42 VDDA(DC) CDACOUT VDDA3 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CDACOUT 100 nF 10 nF SCLK VSSA(CD) SVHS
3
16 5 27
4
L(1) L(1)
68 L(1)
Y
150 k 100 nF VDDA2 L M SMP_CLK (to power supply) P0 P1 VDDD digital ground analog ground 100 nF VDDD RESET_DSP (from C) VDDA3 100 nF VDDA3 100 nF
Green
6 1 7 2 12 8 3 9 4 10 5 15 14 13 11
L(1) L(1)
68 L(1)
C
U, Blue
L(1) L(1)
68 L(1)
V, Red
CVBS
CVBS-RCA
MGK394
(1) Values depend on DSP output configuration.
Fig.19 SAA8110G system configuration for camera application (continued from Fig.18).
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA8110G
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X A A2 A1
Q (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.25 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.7 0.3 Q 0.70 0.58 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 4 0o
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-03-24 95-12-19
1997 Jun 13
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Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA8110G
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Jun 13
31
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA8110G
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 13
32
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
NOTES
SAA8110G
1997 Jun 13
33
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
NOTES
SAA8110G
1997 Jun 13
34
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for cameras
NOTES
SAA8110G
1997 Jun 13
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp36
Date of release: 1997 Jun 13
Document order number:
9397 750 01576

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